The present invention generally relates to a layout method of a semiconductor device, and, more particularly, to an improved layout method of wirings for connecting pads and I/O (input/output) terminals of an I/O buffer in an ASIC (application specific integrated circuit), such as an E/A (embedded array) or a G/A (gate array).
In recent years, in line with large scale, high integration of semiconductor devices, the need to shorten the development period of semiconductor devices has grown. In particular, in ASIC devices, products that meet various specifications need to be developed in a short time using existing chip frames.
Referring to FIGS. 1 and 2, a conventional semiconductor device (LSI) 1 which uses an ASIC (semi-custom IC), such as an E/A and a G/A, is shown.
FIG. 1 is a schematic diagram of part of an existing (fixed or general-purpose) chip frame 2 of the LSI 1 and an LSI package 11. The chip frame 2 is equipped with an I/O region 4 and a pad region 7, each of which extends along a chip side 1a. I/O buffers 3 are arranged in the I/O region 4 and LSI I/O terminals (pads) 6 are arranged in the pad area 7. I/O terminals 8 are defined in the respective I/O buffers 3. The chip frame 2 is further equipped with inter-I/O-pad wirings 9 that connect the I/O terminals 8 and the pads 6. The pads 6 are then connected to lead frames 14 via bonding wires 15.
The I/O region 4 and the number of I/O buffers 3 are set to be fixed or generalized in accordance with the I/O frame information. The pad region 7, and the number of pads 6 and their positions are set to be fixed or generalized in accordance with the pad information. The patterns of the I/O terminals 8 and the patterns of the inter-I/O-pad wirings 9 are set to be fixed or generalized in accordance with wiring information.
The wiring information includes the information for forming the I/O terminals 8 in the I/O buffers 3 toward the pad region 7 along the chip side 1a. The wiring information also includes the information for forming the inter-I/O-pad wirings 9 between the pads 6 and the I/O terminals 8 in the substantially vertical direction for the chip side 1a.
In the LSI 1 equipped with the existing chip frame 2, each pattern is set to be fixed or generalized. Hence, the fixing or generalization of an evaluation board used in a characteristic evaluation test of the chip state is enabled. Accordingly, use of the existing chip frame 2 is effective for reducing the LSI development cost and shortening the LSI development and preparation period.
FIG. 2 is a schematic diagram of the semiconductor device in which the LSI 1 is installed in the LSI package 11. In FIG. 2, the chip side (top side) 1a is mainly described.
The number of pads 6 is automatically determined based on chip size, and the chip size is determined based on the circuit scale of an internal logic circuit 13. Accordingly, as shown in FIG. 2, if the number of required I/O buffers 3 is small irrespective of a relatively large chip size, a chip is installed in a package having less lead frames than the number of pads 6. In this case, there are non-connection (NC) pads 6a that are not connected to the lead frames 14 via bonding wires 15. Further, in terms of the layout of the pads 6 and the lead frames 14, the pads 6 are alternately connected to the lead frames 14 in the vicinity of the right and left ends of the chip side 1a.
Returning again to FIG. 1, the I/O buffers 3 include multi-pin I/O buffers 3a1 and 3a2 having a plurality (for example, two) I/O terminals 8.
For example, the 2-pin I/O buffer 3a1 arranged in region A is formed using two basic I/O frames 5. The 2-pin I/O buffer 3a2 arranged in region B is formed using three basic I/O frames 5. In other words, in region B, because the two I/O terminals 8 are connected to the two pads 6 on both sides of the NC pad 6a, respectively, three basic I/O frames 5 are required.
Accordingly, the pattern data of the two independent I/O buffers that correspond to the 2-pin I/O buffers 3a1 and 3a2 having the same functions and different physical patterns is stored in the data library of a layout device.
As described above, the existence of the NC pad 6a requires the pattern data of the 2-pin I/O buffers 3a1 and 3a2 having the same functions and different physical patterns. In other words, the two types of pattern data of the 2-pin I/O buffers 3a1 and 3a2 need to be prepared separately.
Further, a CAD system used to create the LSI 1 stores the pattern data of the 2-pin I/O buffers 3a1 and 3a2 in the library and reads and processes their pattern data from the library during the design stage. Accordingly, the processing time of the pattern data is prolonged. As a result, the manufacturing cost is increased and the development cycle is prolonged.
It is an object of the present invention to provide a layout method of a semiconductor device that reduces the manufacturing cost and shortens the development period.